Many communication systems, for example, but not limited to, optical communication systems, may be subject to signal distortion and/or inter-symbol interference (ISI), which may be introduced by such effects as dispersion and/or distortion encountered during transmission over a medium (e.g., but not limited to, an optical fiber). In the case of optical fiber communications, for example, polarization mode dispersion may cause such distortion/ISI. Another example of distortion in optical fiber communication systems may be polarization transients, e.g., due to lightning strikes (this may typically happen when an optical fiber is disposed within a ground wire on electrical poles/towers; when lightning strikes, it may have the effect of inducing a magnetic field that may rotate the polarization of light traveling through the fiber; because of the large electrical current and the speed of a lightning strike, the induced polarization rotation rate may be very high (and is known to be highest in fiber-optic channels) and may generally result in data loss in most commercial fiber transmission systems, which generally do not address this problem). Typical communication systems may mitigate the effects of distortion/ISI using various types of equalizers, which are signal filtering systems that may be designed to compensate for non-ideal channels, signal distortion, ISI, polarization transients, etc. However, some types of distortion/ISI, including, for example, polarization transients due to lightning strikes, may result in a quickly-varying channel, which may thus be best served by a quickly-adapting equalizer.
Many equalizers include some type of tapped delay-line filter, e.g., as shown in FIG. 1, which may have coefficients (ci) that may be multiplied by the incoming signal samples (vi), and in which the multiplication results may be summed (note that the “D” in FIG. 1 may represent a unit time delay, but this is not intended to be limiting, and other delays may be possible). Note that the signal samples and the coefficients may be real numbers or, more generally, complex numbers. Some equalizers may have multiple tapped delay-line filters, e.g., where one of the filters may be used to filter results obtained from the other filter, e.g., but not limited to, for purposes of feedback. Other equalizer structures are may also be possible, including frequency-domain implementations, in which the incoming signal samples may be transformed, e.g., using a fast-Fourier transform (FFT) block, into a frequency-domain signal and the coefficients may be determined in the frequency domain, and block multiplication of the frequency-domain signal and coefficients may be implemented, e.g., using block overlap-and-save or block overlap-and-add techniques (as are well-known in the art) to arrive at the same result (the immediate result may be in the frequency domain and may be transformed back to the time domain, e.g., using an inverse FFT (IFFT) block).
Some equalizers are adaptive equalizers, in which filter coefficients (e.g., the ci of FIG. 1) may be adjusted to better mitigate the various deleterious effects, e.g., those discussed above. An adaptive equalizer may use some algorithm to adjust the weights. Some examples of adaptive equalizers may include, but are not limited to, decision-feedback equalizers, adaptive zero-forcing equalizers, mean-square-error (MSE) adaptive equalizers, and least-mean-square (LMS) adaptive equalizers.
FIG. 2 shows an example of a structure of a generic equalizer using decision detected error and the input signal samples to update the filter coefficients (i.e., weights; also referred to as “taps” or “tap-weights”). FIG. 2 shows a filter 21. Filter 21 may be implemented as a digital filter having weights, e.g., an finite impulse response (FIR) filter or an infinite impulse response (IIR) filter; such filters may be implemented by means of a programmed processing device and/or using discrete components, such as adders and multipliers, i.e., in the form of a circuit, and which may be implemented in the time domain or in the frequency domain, as discussed above). FIG. 2 further shows a decision device/circuit 22 that may be used to decide a value for a received bit or symbol. Such decision device/circuit 22 may be, e.g., but is not limited to, a comparator (which may be a multi-level comparator (which may include or be implemented in the form of a maximum-of or minimum-of determiner)) or other decision device (which, similarly, may be implemented using discrete electrical components, as a circuit), a symbol de-mapper (including a device for making a symbol decision, such as a bi-level or multi-level comparator), which may be preceded by various hardware or software designed to compute a decision variable, and which may include multipliers, adders, etc., and/or a processor executing software; this may be performed in complex space and may involve, for example, determining a nearest neighbor (out of known candidate symbols values in a complex symbol space) to received complex symbol values, or the like). According to some aspects of this disclosure, decision device/circuit 22 (and similar components in FIGS. 3, 4, 6A, 6B and 9D) may perform an error determination, based on blind or non-blind equalization techniques, and provide an error value as an output, which may be input to tap-weight updater 23 (or otherwise, tap-weight updater 23 may determine the error value, as discussed below). Finally, FIG. 2 also shows a tap-weight updater 23. The updated tap weights may be derived as a function of the input samples and the output samples (or, in the case of FIG. 2, as a function of the input samples and the decision outputs from block 22). For example, updates may be determined as a function (which may be a vector function) of one or more differences between inputs and outputs (which may be sets of inputs and outputs), which differences may be squared, and may be applied to a previous set of tap weights (e.g., by adding such a function, which may be weighted by a constant or vector weight, for example, to previous tap weights). It should be noted that, in the alternative aspect discussed above, in which the decision device/circuit 22 provides error output, the difference(s) may be the output(s) of decision device/circuit 22 (and, again, this applies to similar components of other figures, as discussed above). The function may be, for example, based on MSE or LMS techniques. These may be implemented, for example, using one or more programmed digital signal processors, combinations of adders and multipliers, etc.
In some communication systems, for example, but not limited to, fiber-optic communication systems, the carrier signal may be subject to, for example, phase noise and/or polarization mode dispersion (PMD). For example, in a fiber-optic communication system, the (optical) carrier signal(s) may be generated by one or more lasers, which may be particularly subject to phase noise. Therefore, as shown in FIG. 3, a carrier recovery device 31 may be inserted, which may remove the phase noise. Carrier recovery techniques and structures for optical communication systems are known in the art; see, e.g., K.-T. Wu et al., “Techniques in Carrier Recovery for Optical Coherent Systems,” OFC/NFOEC Technical Digest, 2012 (hereinafter, “Wu et al.”); T. Xu et al., “Analytical Investigations on Carrier Phase Recovery in Dispersion-Unmanaged n-PSK Coherent Optical Communication Systems,” accepted for publication in Photonics, available for online download as of Aug. 23, 2016; T. Xu et al., “Digital Adaptive Carrier Phase Estimation in Multi-Level Phase Shift Keying Coherent Optical Communication Systems,” IEEE Int'l Conf. on Info. Sci. and Control Eng., 2016; E. Ip et al., “Coherent Detection in Optical Fiber Systems,” Optics Express, Vol. 16, No. 2, Jan. 21, 2008; and T. Xu et al., “Comparative Study on Carrier Phase Estimation Methods in Dispersion-Unmanaged Optical Transmission Systems,” 2016.
In an example implementation, as shown in FIG. 4, a delay 41 may need to be inserted, in order to compensate for the delays introduced by carrier recovery 31 and decision device 22 (in many cases, the delay introduced by decision device 22 may be negligible, relative to delay introduced by carrier recovery 31; but this disclosure is not thus limited). That is, it may be necessary to ensure that the input samples are coordinated with corresponding decision samples, such that corresponding samples reach the tap updater 23 at substantially the same time. This delay (i.e., on both sides of the equalizer) may determine the speed with which the taps can be updated and thus the maximum speed of channel change that can be equalized. Note that delay 41 may be implemented as a delay circuit (e.g., shift register, flip-flop(s), or other delay-inducing circuits/devices) or in software, in the case of a software-based implementation. It may be desirable to reduce the delay (delay 41 and delay introduced by carrier recovery 31 and decision device 22) in order to be able to adapt the equalizer more quickly, e.g., to mitigate fast polarization transients and/or other channel effects.